1. Field of the Invention
The present invention relates generally to dielectric layers formed within microelectronics fabrications. More particularly, the present invention relates to methods for forming vias through dielectric layers formed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and conductor element dimensions have decreased, it has become more common within the art of microelectronics fabrications to form interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications low dielectric constant microelectronics dielectric layers. Low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically formed from low dielectric constant dielectric materials such as but not limited to silsesquioxane spin-on-glass (SOG) dielectric materials and organic polymer spin-on-polymer dielectric materials. Particularly prevalent in the art of microelectronics fabrication are low dielectric constant dielectric layers formed through spin coating and thermal curing of silsesquioxane spin-on-glass (SOG) dielectric materials.
Silsesquioxane spin-on-glass (SOG) dielectric materials are characterized by the general chemical formula R1--Si(OR2)3, where: (1) R1 may be any of several radicals, including but not limited to hydrogen radical and carbon bonded organic radicals, but not oxygen bonded radicals; and (2) R2 is typically, although not exclusively, a carbon bonded organic radical such as but not limited to a methyl radical (--CH3) and an ethyl radical (--C2H5). Such silsesquioxane spin-on-glass (SOG) dielectric materials are typically spin-coated and subsequently thermally cured at temperatures of from about 400 to about 500 degrees centigrade to form within microelectronics fabrications low dielectric constant dielectric layers.
Low dielectric constant dielectric layers formed from silsesquioxane spin-on-glass (SOG) dielectric materials are desirable interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications since there is thus typically efficiently and manufacturably formed a microelectronics fabrication with enhanced microelectronics fabrication circuit speed, decreased patterned microelectronics conductor layer parasitic capacitance and decreased patterned microelectronics conductor layer cross-talk. While low dielectric constant dielectric layers formed from silsesquioxane spin-on-glass (SOG) dielectric materials within microelectronics fabrications are thus desirable within the art of microelectronics fabrication, low dielectric constant dielectric layers are not formed entirely without problems from silsesquioxane spin-on-glass (SOG) dielectric materials within microelectronics fabrications.
In particular, it is known in the art of microelectronics fabrication that when forming through a low dielectric constant dielectric layer formed from a silsesquioxane spin-on-glass (SOG) dielectric material a via through use of a conventional fluorine containing plasma etch method employing an etchant gas composition comprising a fluorine containing etchant gas, such as but not limited to a fluorocarbon fluorine containing etchant gas, there is typically formed upon a sidewall of the via formed through the low dielectric constant dielectric layer a fluorocarbon polymer residue layer which when subsequently simultaneously removed through an oxygen containing plasma stripping method along with a patterned photoresist layer employed in defining the via laterally etches the low dielectric constant dielectric layer exposed within the via to form a laterally etched via. A series of schematic cross-sectional diagrams illustrating the results of progressive stages in forming such a laterally etched via within such a low dielectric constant dielectric layer which in part defines the laterally etched via is shown within the schematic cross-sectional diagrams of FIG. 1 to FIG. 3.
Shown in FIG. 1 is a substrate 10 employed within a microelectronics fabrication, where the substrate 10 has formed thereupon a blanket low dielectric constant dielectric layer 12 formed from a silsesquioxane spin-on-glass (SOG) dielectric material. There is in turn formed upon the blanket low dielectric constant dielectric layer 12 a blanket silicon containing dielectric layer 14 which is typically formed of a silicon containing dielectric material such as but not limited to a silicon oxide dielectric material, a silicon nitride dielectric material or a silicon oxynitride dielectric material. Finally, there is formed upon the blanket silicon containing dielectric layer 14 a pair of patterned photoresist layers 16a and 16b.
Referring now to FIG. 2, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1. Shown in FIG. 2 is schematic cross-sectional diagram of a microelectronics fabrication otherwise equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein the blanket silicon containing dielectric layer 14 and the blanket low dielectric constant dielectric layer 12 have been sequentially patterned through use of a fluorine containing etching plasma 18, while employing the patterned photoresist layers 16a and 16b as an etch mask, to form: (1) the corresponding patterned silicon containing dielectric layers 14a and 14b; and (2) the corresponding patterned low dielectric constant dielectric layers 12a and 12b, which in the aggregate define a via 15 accessing the substrate 10. Upon the sidewalls of the via 15 there is formed a pair of fluorocarbon polymer residue layers 20a and 20b.
The fluorocarbon polymer residue layers 20a and 20b typically derive from fluorine and carbon within a fluorocarbon etchant gas composition employed within the fluorine containing etching plasma 18, if a fluorocarbon etchant gas composition is employed therein, or in the alternative from fluorine within the fluorine containing etchant gas composition along with carbon which may be obtained through slight etching of the patterned photoresist layers 16a and 16b.
Referring now to FIG. 3, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2. Shown in FIG. 3 is a schematic cross-sectional diagram of a microelectronics fabrication in-part otherwise equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2, but wherein the patterned photoresist layers 16a and 16b, and the fluorocarbon polymer residue layers 20a and 20b, have been stripped from the microelectronics fabrication through use of an oxygen containing stripping plasma 22 typically employing conventional oxygen containing stripping plasma conditions including a reactor chamber pressure of from about 10 to about 20 torr. In the process of stripping from the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2 the patterned photoresist layers 16a and 16b, and the fluorocarbon polymer residue layers 20a and 20b, to form the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 3, there is simultaneously typically also laterally etched the patterned low dielectric constant dielectric layers 12a and 12b exposed within the via 15 sidewalls to form the laterally etched low dielectric constant dielectric layers 12a' and 12b' as illustrated in FIG. 3, which in conjunction with the patterned silicon containing dielectric layers 14a and 14b define a laterally etched via 15'.
Microelectronics fabrications analogous or equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 3 are undesirable within the art of microelectronics fabrication since it is often difficult to subsequently form void free microelectronics layers, such as but not limited to void free patterned microelectronics conductor stud layers, within undercut vias such as the laterally etched via 15'. It is thus towards the goal of forming within a microelectronics fabrication through a fluorine containing plasma etch method a via through a low dielectric constant dielectric layer formed of a silsesquioxane spin-on-glass (SOG) dielectric material while attenuating lateral etching of the via when stripping from the microelectronics fabrication through an oxygen containing plasma stripping method a patterned photoresist layer employed in defining the via and a fluorocarbon polymer residue layer formed upon a sidewall of the via incident to the fluorine containing plasma etch method, that the present invention is generally directed.
Various novel plasma etch methods and materials have been disclosed in the art of microelectronics fabrication.
For example, Shinagawa et al., in U.S. Pat. No. 4,961,820, discloses an oxygen containing plasma stripping method for stripping from an integrated circuit microelectronics fabrication a photoresist layer employed in fabricating the integrated circuit microelectronics fabrication. The method employs a reactant gas composition comprising oxygen, water vapor or hydrogen and an additional gas in proportions such that: (1) a stripping rate of the photoresist layer is higher than observed with an otherwise equivalent reactant gas composition absent the additional gas; and (2) an activation energy of the photoresist layer stripping reaction is lower than an activation energy of the photoresist layer stripping reaction absent the additional gas.
In addition, Jolly et al., in U.S. Pat. No. 5,269,880, discloses: (1) a method for forming through an insulator layer within an integrated circuit microelectronics fabrication a via with tapered sidewalls, which via accesses a conductor layer within the integrated circuit microelectronics fabrication; and (2) the integrated circuit microelectronics fabrication having formed therein the insulator layer having formed therethrough the via with the tapered sidewalls, which via accesses the conductor layer within the integrated circuit microelectronics fabrication.
The method employs a protective layer formed over an insulator layer having a steep sided via formed therethrough, which steep sided via accesses the conductor layer, where the protective layer is additionally formed upon the steep sided via sidewalls and the conductor layer, and where the protective layer and part of the insulator layer are subsequently removed through a sputter etch method to form from the steep sided via the via with the tapered sidewalls.
Further, Jones et al., in U.S. Pat. No. 5,380,401, discloses a method for removing from aluminum containing bond pads within integrated circuit microelectronics fabrications aluminum/fluorine/oxide residues which otherwise impede formation of fully functional or reliable electrical connections to those aluminum containing bond pads. The method employs an argon plasma etching of the aluminun/fluorine/oxide residues, the argon plasma optionally employing a carrier gas such as carbon dioxide, or an inert gas such as helium, neon, krypton or xenon.
Yet further, Wu et al., in U.S. Pat. No. 5,432,073, discloses a method for forming within vias formed through spin-on-glass (SOG) dielectric layers within integrated circuit microelectronics fabrications patterned metal conductor interconnection layers which access lower lying patterned conductor layers within the integrated circuit microelectronics fabrications. The method employs an argon plasma etching of a residual polymer layer and a native oxide layer formed upon the lower lying patterned conductor layer, followed by degassing the spin-on-glass (SOG) layer exposed within the via sidewall prior to forming the patterned conductor metal interconnection layer within the via.
Finally, Mihara et al., in U.S. Pat. No. 5,560,803, discloses a method for oxygen plasma ashing with a uniform ashing rate a photoresist layer from upon a semiconductor substrate within an integrated circuit microelectronics fabrication ashed within a plasma reactor chamber. The method employs providing and maintaining a flow of a non-activated oxygen containing gas within the plasma reactor chamber before either generating a plasma within the plasma reactor chamber or ashing the photoresist layer within the plasma reactor chamber.
Desirable in the art of microelectronics fabrication are fluorine containing plasma etch methods through which a via may be formed through a low dielectric constant dielectric layer formed of a silsesquioxane spin-on-glass (SOG) dielectric material within a microelectronics fabrication with attenuated lateral etching of the via when stripping from the microelectronics fabrication through an oxygen containing plasma stripping method a patterned photoresist layer employed in defining the via and a fluorocarbon polymer residue layer formed upon the via sidewall incident to the fluorine containing plasma etch method. Particularly desirable within the art of integrated circuit microelectronics fabrication are fluorine containing plasma etch methods through which a via may be formed through a low dielectric constant dielectric layer formed of a silsesquioxane spin-on-glass (SOG) dielectric material within an integrated circuit microelectronics fabrication with attenuated lateral etching of the via when stripping from the integrated circuit microelectronics fabrication through an oxygen containing plasma stripping method a patterned photoresist layer employed in defining the via and a fluorocarbon polymer residue layer formed upon the via sidewall incident to the fluorine containing plasma etch method. It is towards these goals that the present invention is both generally and more specifically directed.